The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Nov. 06, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shay Gueron, Haifa, IL;

Vlad Krasnov, Nesher, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/06 (2006.01); G06F 9/30 (2018.01); G09C 1/00 (2006.01); G06F 21/72 (2013.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
H04L 9/0643 (2013.01); G06F 9/3001 (2013.01); G06F 9/30007 (2013.01); G06F 9/3016 (2013.01); G06F 9/30018 (2013.01); G06F 9/30036 (2013.01); G06F 9/3895 (2013.01); G06F 21/72 (2013.01); G09C 1/00 (2013.01); H04L 2209/125 (2013.01);
Abstract

A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words A, B, C, D, E, F, G, and Hthat are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words A, B, E, and F, which are to correspond to a round (j+2) of the SM3 hash algorithm.


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