The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Dec. 31, 2019
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Jie Chang, Suzhou, CN;

HuiBin Chen, Suzhou, CN;

Keunhyuk Lee, Suzhou, CN;

Jerome Tysseyre, Scottsdale, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/473 (2006.01); H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2006.01); H01L 25/11 (2006.01); H01L 25/00 (2006.01); H01L 23/433 (2006.01); H01L 23/495 (2006.01); H02M 7/5387 (2007.01); H02M 7/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 23/3114 (2013.01); H01L 23/3735 (2013.01); H01L 23/4334 (2013.01); H01L 23/473 (2013.01); H01L 23/49551 (2013.01); H01L 24/32 (2013.01); H01L 25/117 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 23/3107 (2013.01); H01L 23/49537 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/14252 (2013.01); H02M 7/003 (2013.01); H02M 7/5387 (2013.01);
Abstract

In one general aspect, a package can include a first submodule including a first semiconductor die coupled to a first substrate and a first spacer, and disposed between the first spacer and the first substrate. The first submodule includes a second spacer disposed lateral to the first semiconductor die. The package includes a second submodule including a second semiconductor die coupled to a second substrate and a third spacer, and disposed between the third spacer and the second substrate. The second submodule includes a fourth spacer disposed lateral to the second semiconductor die. The package includes an inter-module layer disposed between the first submodule and the second submodule. The first spacer of the first submodule is electrically coupled to the fourth spacer of the second-submodule via the inter-module layer. The second spacer of the first submodule is electrically coupled to the third spacer of the second-submodule via the inter-module layer.


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