The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

May. 09, 2017
Applicants:

King Abdullah University of Science and Technology, Thuwal, SA;

King Abdulaziz City for Science and Technology, Riyadh, SA;

Inventors:

Chao Zhao, Thuwal, SA;

Tien Khee Ng, Thuwal, SA;

Lain-Jong Li, Thuwal, SA;

Boon Siew Ooi, Thuwal, SA;

Ahmed Y. Alyameni, Riyadh, SA;

Munir M. Eldesouki, Riyadh, SA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/267 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02485 (2013.01); H01L 21/02425 (2013.01); H01L 29/068 (2013.01); H01L 29/0676 (2013.01); H01L 29/267 (2013.01); H01L 21/0254 (2013.01); H01L 21/02603 (2013.01); H01L 23/29 (2013.01);
Abstract

Methods of direct growth of high quality group III-V and group III-N based materials and semiconductor device structures in the form of nanowires, planar thin film, and nanowires-based devices on metal substrates are presented. The present compound semiconductor all-metal scheme greatly simplifies the fabrication process of high power light emitters overcoming limited thermal and electrical conductivity of nanowires grown on silicon substrates and metal thin film in prior art. In an embodiment the methods include: (i) providing a metal substrate; (ii) forming a transition metal dichalcogenide (TMDC) layer on a surface of the metal substrate; and (iii) growing a semiconductor epilayer on the transition metal dichalcogenide layer using a semiconductor epitaxy growth system. In an embodiment, the semiconductor device structures can be compound semiconductors in contact with a layer of metal dichalcogenide, wherein the layer of metal dichalcogenide is in contact with a metal substrate.


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