The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Sep. 27, 2018
Applicant:

Crossbar, Inc., Santa Clara, CA (US);

Inventors:

Mehdi Asnaashari, Danville, CA (US);

Hagop Nazarian, San Jose, CA (US);

Christophe Sucur, San Jose, CA (US);

Sylvain Dubois, San Francisco, CA (US);

Assignee:

Crossbar, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 7/18 (2006.01); G11C 8/12 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 8/14 (2006.01); G06F 17/16 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G06F 17/16 (2013.01); G11C 7/18 (2013.01); G11C 8/12 (2013.01); G11C 8/14 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0097 (2013.01); G11C 2029/0411 (2013.01); G11C 2213/71 (2013.01); G11C 2213/75 (2013.01); G11C 2213/79 (2013.01);
Abstract

Provided herein resistive random access memory matrix multiplication structures and methods. A non-volatile memory logic system can comprise a bit line and at a set of wordlines. Also included can be a set of resistive switching memory cells at respective intersections between the bit line and the set of wordlines. The set of resistive switching memory cells are programmed with a value of an input data bit of a first data matrix and receive respective currents on the set of wordlines. The respective currents comprise respective values of an activation data bit of a second data matrix. A resulting value based on a matrix multiplication corresponds to an output value of the bit line.


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