The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Sep. 04, 2018
Applicants:

University of Maryland AT College Park, College Park, MD (US);

Crossbar, Inc., Santa Clara, CA (US);

Inventors:

Donald Yeung, Bethesda, MD (US);

Bruce L. Jacob, Annapolis, MD (US);

Mehdi Asnaashari, Danville, CA (US);

Sylvain Dubois, San Francisco, CA (US);

Assignee:

Crossbar, Inc, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G06F 12/0802 (2016.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G11C 13/003 (2013.01); H01L 27/2463 (2013.01); G06F 2212/1021 (2013.01);
Abstract

Disclosed is a monolithic integrated circuit (IC) computing device with multiple independent process cores (multicore) and embedded, non-volatile resistive memory serving as system memory. The resistive system memory is fabricated above the substrate, and logic circuits embodying the process cores are fabricated on the substrate. In addition, access circuitry for operating on the resistive system memory, and circuitry embodying memory controllers, routing devices and other logic components is provided at least in part on the substrate. Large main memory capacities of tens or hundreds of gigabytes (GB) are provided and operable with many process cores, all on a single die. This monolithic integration provides close physical proximity between the process cores and main memory, facilitating significant memory parallelism, reduced power consumption, and eliminating off-chip main memory access requests.


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