The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 21, 2021

Filed:

Jun. 03, 2020
Applicant:

Dyi-chung HU, Hsinchu, TW;

Inventor:

Dyi-Chung Hu, Hsinchu, TW;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 1/073 (2006.01); G01R 31/28 (2006.01); H01L 21/78 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); G01R 3/00 (2006.01);
U.S. Cl.
CPC ...
G01R 1/07378 (2013.01); G01R 3/00 (2013.01); G01R 31/2884 (2013.01); G01R 31/2886 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01);
Abstract

An integrated substrate for testing a semiconductor wafer and a method are provided. The integrated substrate includes a first redistribution structure including a fine redistribution circuitry, a plurality of testing tips disposed on a first surface of the first redistribution structure and electrically connected to the fine redistribution circuitry to probe the semiconductor wafer, a second redistribution structure including a coarse redistribution circuitry and disposed over a second surface of the first redistribution structure opposite to the first surface, and a plurality of conductive joints interposed between the coarse redistribution circuitry and the fine redistribution circuitry to provide electrical connections therebetween. A layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry.


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