The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2021
Filed:
Oct. 11, 2019
Seeqc, Inc., Elmsford, NY (US);
Daniel Yohannes, Stamford, CT (US);
Denis Amparo, White Plains, NY (US);
Oleksandr Chernyashevskyy, White Plains, NY (US);
Oleg Mukhanov, Putnam Valley, NY (US);
Mario Renzullo, Yonkers, NY (US);
Andrei Talalaeskii, Mahopac, NY (US);
Igor Vernik, Yorktown Heights, NY (US);
John Vivalda, Poughkeepsie, NY (US);
Jason Walter, Trumbull, CT (US);
Other;
Abstract
A method for bonding two superconducting integrated circuits ('chips'), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.