The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Sep. 16, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Bo-Shiun Chen, Taichung, TW;

Chun-Jen Chen, Tainan, TW;

Chung-Ting Huang, Kaohsiung, TW;

Chi-Hsuan Tang, Kaohsiung, TW;

Jhong-Yi Huang, Nantou County, TW;

Guan-Ying Wu, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/15 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/02532 (2013.01); H01L 21/02587 (2013.01); H01L 29/0847 (2013.01); H01L 29/157 (2013.01); H01L 29/66522 (2013.01);
Abstract

A transistor with strained superlattices as source/drain regions includes a substrate. A gate structure is disposed on the substrate. Two superlattices are respectively disposed at two sides of the gate structure and embedded in the substrate. The superlattices are strained. Each of the superlattices is formed by a repeated alternating stacked structure including a first epitaxial silicon germanium and a second epitaxial silicon germanium. The superlattices serve as source/drain regions of the transistor.


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