The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Nov. 10, 2016
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Binghua Hu, Plano, TX (US);

Abbas Ali, Plano, TX (US);

Sopa Chevacharoenkul, Richardson, TX (US);

Jarvis Benjamin Jacobs, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 21/762 (2006.01); H01L 21/265 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 28/40 (2013.01); H01L 21/26513 (2013.01); H01L 21/3081 (2013.01); H01L 21/76224 (2013.01);
Abstract

A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.


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