The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 14, 2021
Filed:
Jan. 13, 2020
Applicant:
Amkor Technology Singapore Holding Pte. Ltd., Singapore, SG;
Inventors:
Jong Sik Paek, Incheon, KR;
No Sun Park, Gwangju-si, KR;
Assignee:
Amkor Technology Singapore Holding Pte. Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 24/73 (2013.01); H01L 24/82 (2013.01); H01L 25/0657 (2013.01); H01L 23/3114 (2013.01); H01L 2224/022 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/2499 (2013.01); H01L 2224/24105 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/25175 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73217 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82 (2013.01); H01L 2224/8203 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/94 (2013.01); H01L 2224/97 (2013.01);
Abstract
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.