The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 14, 2021

Filed:

Aug. 06, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Shankar Natarajan, Folsom, CA (US);

Suresh Nagarajan, Folsom, CA (US);

Shivashekar Muralishankar, Folsom, CA (US);

Sriram Natarajan, Folsom, CA (US);

Yihua Zhang, Cupertino, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0634 (2013.01); G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G11C 11/5628 (2013.01);
Abstract

An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.


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