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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11114527 B1

PDFFull Text
Date of Patent:
Sep. 07, 2021

Filed:

Mar. 11, 2020

Semiconductor device and method for manufacturing same

Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Makoto Koshimizu, Tokyo, JP;

Hideki Niwayama, Tokyo, JP;

Kazuyuki Umezu, Tokyo, JP;

Hiroki Soeda, Tokyo, JP;

Atsushi Tachigami, Tokyo, JP;

Takeshi Iijima, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Tokyo, JP;

Attorney:

Foley & Lardner LLP

Primary Examiner:

David C Spalla

Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/76205 (2013.01); H01L 21/76224 (2013.01); H01L 21/82385 (2013.01); H01L 21/823857 (2013.01); H01L 21/823878 (2013.01); H01L 27/0922 (2013.01); H01L 29/0661 (2013.01); H01L 29/42368 (2013.01); H01L 29/66659 (2013.01); H01L 29/66689 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H01L 29/0638 (2013.01); H01L 29/0653 (2013.01); H01L 29/0696 (2013.01); H01L 29/086 (2013.01); H01L 29/0878 (2013.01); H01L 29/1083 (2013.01); H01L 29/41758 (2013.01); H01L 29/4238 (2013.01); H01L 29/456 (2013.01); H01L 29/4933 (2013.01); H01L 29/665 (2013.01);
Abstract

A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.

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