The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Sep. 25, 2019
Applicant:

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd., Hubei, CN;

Inventors:

Yang Li, Hubei, CN;

Sheng Hu, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/78 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/78 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 24/08 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 24/89 (2013.01); H01L 24/94 (2013.01); H01L 25/50 (2013.01); H01L 28/60 (2013.01); H01L 24/29 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/29187 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/83896 (2013.01); H01L 2225/06531 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/04642 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01);
Abstract

A wafer structure, a method for manufacturing the same and a chip structure are provided. A first capacitor plate is arranged in a first chip, a second capacitor plate is arranged in a second chip, and the first chip is stacked together via bonding layers with the second chip with a front surface of the first chip facing toward a front surface of the second chip. In this way, a capacitor structure formed by the first capacitor plate, the second capacitor plate and dielectric materials provided therebetween is formed while bonding the first chip and second chip together, and the capacitor plate and the dielectric materials may be formed while forming a device interconnection structure in the chip, such that no additional process is required, thereby improving device integration and process integration.


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