The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Nov. 27, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joshua M. Rubin, Albany, NY (US);

Steven Lorenz Wright, Tucson, AZ (US);

Lawrence A. Clevenger, Saratoga Springs, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 21/02013 (2013.01); H01L 21/02016 (2013.01); H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 2224/02371 (2013.01); H01L 2924/18162 (2013.01);
Abstract

Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.


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