The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2021
Filed:
Feb. 22, 2019
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Balaji Srinivasan, Folsom, CA (US);
Sandeep K. Guliani, Folsom, CA (US);
DerChang Kau, Cupertino, CA (US);
Ashir G. Shah, El Dorado Hills, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/10 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 8/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01);
Abstract
A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.