The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Oct. 29, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Sandeep Kumar Goel, Dublin, CA (US);

Yun-Han Lee, Hsinchu County, TW;

Vinay Kotha, San Jose, CA (US);

Ankita Patidar, Dublin, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 17/18 (2006.01); G06N 20/00 (2019.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 17/18 (2013.01); G06F 30/398 (2020.01); G06N 20/00 (2019.01);
Abstract

Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of electronic circuitry for an electronic device. The electronic device includes scan flip-flops to autonomously test the electronic circuitry for various manufacturing faults. The EDA of the present disclosure statistically groups the scan flip-flops into scan chains in such a manner such that scan flip-flops within each scan chain share similar characteristics, parameters, or attributes. Thereafter, the EDA of the present disclosure intelligently arranges ordering for the scan flip-flops within each of the scan chains to optimize power, performance, and/or area of the electronic circuitry.


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