The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Sep. 28, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ning Cheng, San Jose, CA (US);

Xiangyong Wang, San Jose, CA (US);

Mahesh A. Iyer, Fremont, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/392 (2020.01); G06F 30/34 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 119/04 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/34 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2119/04 (2020.01);
Abstract

An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance.


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