The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Mar. 13, 2018
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Ashutosh Varma, Milpitas, CA (US);

Cédric Marie Frédéric René Babled, La Gaude, FR;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/331 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/331 (2020.01);
Abstract

A hybrid emulation system and method for hybrid emulation of a design under test (DUT). The DUT has system memory logically segmented into a plurality of memory blocks. The hybrid emulation system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. At least one of the hardware emulation system or the simulation system is configured to assign a memory block of the plurality of memory blocks to one of the hardware emulation system or the simulation system based on memory access statistics describing accesses to the memory block during the hybrid emulation.


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