The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 2021

Filed:

Dec. 10, 2015
Applicants:

National Taiwan University, Taipei, TW;

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Wen-Li Shih, Taipei, TW;

Jenq-Kuen Lee, Hsinchu, TW;

Cheng-Yen Lin, Chiayi County, TW;

Ming-Yu Hung, Nantou County, TW;

Assignees:

National Taiwan University, Taipei, TW;

MFDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/28 (2006.01); G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 1/28 (2013.01); G06F 8/4432 (2013.01); Y02D 10/00 (2018.01);
Abstract

A probabilistic framework for compiler optimization with multithread power-gating controls includes scheduling all thread fragments of a multithread computer code with the estimated execution time, logging all time stamps of events, and sorting and unifying the logged time stamps. Time slices are constructed using adjacent time stamps of each thread fragment. A power-gating time having a component turned off for each time slice is determined. Power-gateable windows that reduce energy consumption of the time slice is determined according to the power-gating time. The compiler inserts predicated power-gating instructions at locations corresponding to the selected power-gateable windows into the power-gateable computer code.


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