The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Feb. 14, 2020
Applicant:

Ibiden Co., Ltd., Ogaki, JP;

Inventors:

Youhong Wu, Ogaki, JP;

Koji Sato, Ogaki, JP;

Yoshihiro Kodera, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/111 (2013.01); H05K 2201/0367 (2013.01); H05K 2201/094 (2013.01); H05K 2201/0939 (2013.01); H05K 2201/09409 (2013.01); H05K 2201/09472 (2013.01); H05K 2201/09745 (2013.01);
Abstract

A method for manufacturing a printed wiring board includes forming a base insulating layer, forming a conductor layer on the base layer, forming a solder resist layer on the base layer such that the resist layer covers the conductor layer, forming first opening exposing a first pad of the conductor layer, forming second opening exposing a second pad of the conductor layer and having diameter smaller than diameter of the first opening, forming a first bump on the first pad, and forming a second bump on the second pad such that the second bump has diameter smaller than diameter of the first bump. The first bump includes a first base plating layer and a first top plating layer, and the second bump includes a second base plating layer and a second top plating layer having upper surface higher than the uppermost position of upper surface of the first top layer.


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