The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Mar. 18, 2020
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventor:

Chia-Fu Chang, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01C 11/00 (2006.01); H03K 19/00 (2006.01); H03K 17/16 (2006.01); H03K 19/0185 (2006.01); H03K 3/356 (2006.01); H03K 19/0944 (2006.01); H03K 17/687 (2006.01); G11C 5/02 (2006.01); G11C 11/16 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/16 (2006.01); G05F 3/26 (2006.01); H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); G11C 5/025 (2013.01); G11C 7/06 (2013.01); G11C 7/1051 (2013.01); G11C 7/1084 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H03K 3/356 (2013.01); H03K 17/162 (2013.01); H03K 17/6871 (2013.01); H03K 19/018528 (2013.01); H03K 19/0944 (2013.01); G05F 3/262 (2013.01); H02M 3/07 (2013.01);
Abstract

A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.


Find Patent Forward Citations

Chang, Chia-Fu. (2021). Memory cell and memory cell array of magnetoresistive random access memory operated by negative voltage (U.S. Patent No. 11108395). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11108395

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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