The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Mar. 25, 2020
Applicant:

Mediatek Singapore Pte. Ltd., Singapore, SG;

Inventors:

Jen-Wei Ko, San Jose, CA (US);

Zheng Zeng, San Jose, CA (US);

Sheng-Yi Huang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7838 (2013.01); H01L 23/5286 (2013.01); H01L 29/0649 (2013.01); H01L 29/1083 (2013.01);
Abstract

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, an N-type well region over the semiconductor substrate, a FDSOI transistor formed over the N-type well region, a first shallow trench isolation (STI) region over the N-type well region, a first N-type doped region over the N-type well region, a second STI region over the semiconductor substrate, a first P-type doped region over the semiconductor substrate, and a first interconnection element over the first P-type doped region. The first P-type doped region is separated from the first N-type doped region by the second STI region. The first interconnection element is configured to connect the first P-type doped region to a ground. No interconnection element is formed over the first N-type doped region so that the first N-type doped region and the N-type well region are floating.


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