The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Jun. 25, 2019
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Daisuke Murata, Tokyo, JP;

Hiroshi Yoshida, Tokyo, JP;

Hidetoshi Ishibashi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/14 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H02M 1/08 (2006.01); H02M 7/5387 (2007.01); H01L 23/31 (2006.01); H02P 27/08 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 21/4803 (2013.01); H01L 21/4846 (2013.01); H01L 23/142 (2013.01); H01L 23/367 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H02M 1/08 (2013.01); H02M 7/53871 (2013.01); H01L 23/3121 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10254 (2013.01); H01L 2924/10272 (2013.01); H02P 27/08 (2013.01);
Abstract

According to the present invention, a semiconductor device includes an insulating substrate having an organic insulating layer and a circuit pattern provided on the organic insulating layer; and a semiconductor chip provided on an upper surface of the circuit pattern, wherein a thickness of the circuit pattern is not less than 1 mm and not more than 3 mm. According to the present invention, a method for manufacturing a semiconductor device includes forming a metal layer with a thickness not less than 1 mm and not more than 3 mm on an organic insulating layer; patterning the metal layer by machining processing to form a circuit pattern; and providing a semiconductor chip on an upper surface of the circuit pattern.


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