The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Dec. 03, 2018
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Shi-You Liu, Kaohsiung, TW;

Tsai-Yu Wen, Tainan, TW;

Ming-Shiou Hsieh, Chiayi County, TW;

Rong-Sin Lin, Taichung, TW;

Ching-I Li, Tainan, TW;

Neng-Hui Yang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28238 (2013.01); H01L 21/0206 (2013.01); H01L 21/2652 (2013.01); H01L 21/324 (2013.01); H01L 21/823892 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.


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