The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Feb. 26, 2020
Applicant:

Tetramem Inc., Newark, CA (US);

Inventors:

Wenbo Yin, Newark, CA (US);

Ning Ge, Newark, CA (US);

Assignee:

TetraMem Inc., Newark, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 13/0023 (2013.01); H01L 27/2436 (2013.01);
Abstract

Technologies relating to crossbar array circuits with nTnR design to reduce sneak current path and minimize area size are disclosed. An example crossbar array circuit includes: a first transistor comprising a first source terminal, a first drain terminal and a first gate terminal; a first RRAM device connected to the first source terminal of the first transistor; a second transistor comprising a second source terminal, a second drain terminal and a second gate terminal; a second RRAM device connected to the second source terminal of the second transistor; a word line connected to the first drain terminal of the first transistor and the second drain terminal of the second transistor; a first bit line connected to the first RRAM device; and a second bit line connected to the second RRAM device, wherein the first gate terminal of the first transistor is configured to be connected to a first selective voltage source, and the second gate terminal is configured to be connected to a second selective voltage source.


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