The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2021
Filed:
May. 04, 2021
Monolithic 3d Inc., Klamath Falls, OR (US);
Zvi Or-Bach, Haifa, IL;
Zeev Wurman, Palo Alto, CA (US);
MONOLITHIC 3D INC., Klamath Falls, OR (US);
Abstract
A method of designing a 3D Integrated Circuit, the method comprising: performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then performing a first placement of said logic strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, wherein said 3D Integrated Circuit comprises through silicon vias for connection between said logic strata and said memory strata; and performing a second placement of said memory strata based on said first placement, wherein said memory comprises a first memory array, wherein said logic comprises a first logic circuit controlling said first memory array, wherein said first placement comprises placement of said first logic circuit, and wherein said second placement comprises placement of said first memory array based on said placement of said first logic circuit.