The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Apr. 02, 2020
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Tadashi Miyakawa, Yokohama Kanagawa, JP;

Katsuhiko Hoya, Yokohama Kanagawa, JP;

Hiroyuki Takenaka, Kamakura Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H01L 43/08 (2006.01); G11C 13/00 (2006.01); H01L 27/22 (2006.01); H01L 23/528 (2006.01); H01L 29/78 (2006.01); H01L 43/02 (2006.01); H01F 10/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H01L 23/528 (2013.01); H01L 29/7827 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01); G11C 2213/72 (2013.01); H01F 10/3254 (2013.01); H01F 10/3286 (2013.01);
Abstract

A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.


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