The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Mar. 16, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jong-youn Kim, Seoul, KR;

Seok-hyun Lee, Hwaseong-si, KR;

Youn-ji Min, Seoul, KR;

Kyoung-lim Suk, Suwon-si, KR;

Seok-won Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 21/683 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 25/0655 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 2221/68345 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/16112 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83104 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/97 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

Provided is a semiconductor package including a semiconductor chip, a molding portion surrounding at least a side surface of the semiconductor chip, a passivation layer including a contact plug connected to the semiconductor chip and having a narrowing width further away from the semiconductor chip in a vertical direction, below the semiconductor chip, and a redistribution layer portion electrically connecting the semiconductor chip with an external connection terminal, below the passivation layer. The redistribution layer portion includes an upper pad connected to the contact plug and a fine pattern positioned at a same level as the upper pad, a redistribution layer and a via plug, which has a widening width further away from the semiconductor chip in the vertical direction, and a lower pad connected to the external connection terminal and exposed to an outside of the semiconductor package in a lower part of the redistribution layer portion.


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