The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Jul. 20, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Andrew Joseph Kelly, Hsinchu County, TW;

Yusuke Oniki, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/67 (2006.01); H01L 21/3063 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01); B82Y 10/00 (2011.01); C25F 3/12 (2006.01); H01L 29/417 (2006.01); C25F 7/00 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01); C25D 17/00 (2006.01); H01L 29/06 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67086 (2013.01); B82Y 10/00 (2013.01); C25D 17/00 (2013.01); C25F 3/12 (2013.01); C25F 7/00 (2013.01); H01L 21/02233 (2013.01); H01L 21/02258 (2013.01); H01L 21/28158 (2013.01); H01L 21/3063 (2013.01); H01L 21/30635 (2013.01); H01L 29/41725 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01); H01L 21/02236 (2013.01); H01L 21/02238 (2013.01); H01L 21/02241 (2013.01); H01L 29/0673 (2013.01); H01L 29/513 (2013.01); H01L 29/665 (2013.01); H01L 29/7853 (2013.01);
Abstract

A method includes depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are stacked alternately; patterning the first and second semiconductor layers to form a fin structure; supplying a first bias to the substrate after patterning the first and second semiconductor layers; and etching the second semiconductor layers when the semiconductor substrate is supplied with the first bias, wherein etching the second semiconductor layers is performed such that the first semiconductor layers are suspended above the substrate.


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