The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Sep. 06, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Patrick Michael Sheridan, Boulder, CO (US);

Assignee:

MICRON TECHNOLOGY, INC., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/1009 (2016.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 12/0646 (2013.01); G06F 2212/657 (2013.01);
Abstract

A method for managing logical-to-physical (L2P) mappings in a memory subsystem is described. The method includes updating, by a set of processing units, an L2P table based on a set of journal pages from the non-volatile memory. The L2P table prior to the update includes a first set of entries from a table snapshot and the table includes a second set of entries following the update from a set of journal pages. Each L2P table entry (1) corresponds to a logical address in a set of logical addresses and (2) includes a physical address of a set of memory components. The set of logical addresses are categorized into zones and each processing unit is assigned to a separate zone such that each processing unit updates the first set of entries based on an assigned zone of a corresponding logical address and each zone includes at least two non-contiguous logical addresses.


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