The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Oct. 31, 2019
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Yanli Zhang, San Jose, CA (US);

Johann Alsmeier, San Jose, CA (US);

Teruo Okina, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11548 (2017.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/11529 (2017.01); H01L 27/11573 (2017.01); H01L 27/11575 (2017.01); H01L 21/768 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11548 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06565 (2013.01);
Abstract

A method of forming a device structure includes forming a memory-level structure including a three-dimensional memory device over a front side surface of a semiconductor substrate, forming memory-side dielectric material layers over the memory-level structure, bonding a handle substrate to the memory-side dielectric material layers, thinning the semiconductor substrate while the handle substrate is attached to the memory-side dielectric material layers, forming a driver circuit including field effect transistors on a backside semiconductor surface of the semiconductor substrate after thinning the semiconductor substrate, and removing the handle substrate from the memory-side dielectric material layers.


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