The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Dec. 14, 2018
Applicant:

Nexperia B.v., Nijmegen, NL;

Inventors:

Leung Chi Ho, Kwai Chung, HK;

Pompeo V. Umali, Kwai Chung, HK;

Shun Tik Yeung, Kwai Chung, HK;

Assignee:

Nexperia B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/565 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3171 (2013.01); H01L 23/3185 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/33 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 23/3114 (2013.01); H01L 24/06 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04026 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05023 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/0556 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/06157 (2013.01); H01L 2224/06187 (2013.01); H01L 2224/325 (2013.01); H01L 2224/96 (2013.01);
Abstract

A semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device may comprise a semiconductor die having a top major surface that has one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces; a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die, wherein the molding material defines a package body that has a top surface and a side surface; wherein the plurality of electrical contacts are exposed on the top surface of the package body and a metal layer is arranged over and electrically connected to the electrical contacts and wherein the metal layer extends to and at least partially covers a side surface of the package body.


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