The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Jan. 28, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Tien-Chun Yang, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/28 (2006.01); H03K 5/24 (2006.01); G11C 7/06 (2006.01); G11C 11/16 (2006.01); G11C 7/00 (2006.01); G11C 7/14 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 29/02 (2006.01); G11C 16/30 (2006.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G11C 16/28 (2013.01); G11C 7/00 (2013.01); G11C 7/062 (2013.01); G11C 7/14 (2013.01); G11C 11/1673 (2013.01); G11C 11/5642 (2013.01); G11C 16/30 (2013.01); G11C 16/349 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); H03K 5/2472 (2013.01); G11C 5/02 (2013.01); G11C 7/065 (2013.01);
Abstract

A sensing circuit includes a current generating circuit and a sensing circuit. The current generating circuit includes a first portion configured to generate a first mirrored current corresponding to a first reference cell programmed to a low logical value, a second portion configured to generate a second mirrored current corresponding to a second reference cell programmed to a high logical value, and a transistor configured to generate a reference voltage by conducting a first reference current equal to a sum of the first mirrored current and the second mirrored current. The sensing circuit includes a sense amplifier configured to generate an output voltage having a logical value based on a second reference current and a cell current of a memory cell, the second reference current being generated from the reference voltage.


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