The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 17, 2021

Filed:

Nov. 27, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsu-Ting Huang, Hsinchu, TW;

Tung-Chin Wu, Hsinchu, TW;

Shih-Hsiang Lo, Hsinchu, TW;

Chih-Ming Lai, Hsinchu, TW;

Jue-Chin Yu, Taichung, TW;

Ru-Gun Liu, Zhubei, TW;

Chin-Hsiang Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/392 (2020.01); G03F 7/20 (2006.01); G06F 16/23 (2019.01); G06N 3/08 (2006.01); G06N 3/04 (2006.01);
U.S. Cl.
CPC ...
G03F 7/70441 (2013.01); G06F 16/2379 (2019.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01);
Abstract

A method for manufacturing a lithographic mask for an integrated circuit includes performing an optical proximity correction (OPC) process to an integrated circuit mask layout to produce a corrected mask layout. The method further includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout. The method also includes performing an inverse lithographic technology (ILT) process to the corrected mask layout to enhance the corrected mask layout to produce an OPC-ILT-enhanced mask layout.


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