The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Dec. 05, 2019
Applicant:

Nexperia B.v., Nijmegen, NL;

Inventors:

Yan Lai, Nijmegen, NL;

Mark Gajda, Nijmegen, NL;

Barry Wynne, Nijmegen, NL;

Phil Rutter, Nijmegen, NL;

Assignee:

NEXPERIA B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7811 (2013.01); H01L 27/0255 (2013.01); H01L 29/0646 (2013.01); H01L 29/49 (2013.01); H01L 29/7808 (2013.01); H01L 29/7813 (2013.01);
Abstract

The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.


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