The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Sep. 03, 2020
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Shih-Yin Hsiao, Chiayi County, TW;

Ching-Chung Yang, Hsinchu, TW;

Kuan-Liang Liu, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/8249 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823425 (2013.01); H01L 21/8249 (2013.01); H01L 21/823437 (2013.01); H01L 27/0251 (2013.01); H01L 29/0607 (2013.01); H01L 29/4238 (2013.01); H01L 29/42368 (2013.01); H01L 29/4925 (2013.01); H01L 29/7832 (2013.01); H01L 29/7835 (2013.01); H01L 29/78 (2013.01);
Abstract

A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.


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