The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Aug. 15, 2019
Applicant:

Asml Netherlands B.v., Veldhoven, NL;

Inventors:

Sunit Sondhi Mahajan, Veldhoven, NL;

Abraham Slachter, Waalre, NL;

Brennan Peterson, Longmont, CO (US);

Koen Wilhelmus Cornelis Adrianus Van Der Straten, Oud Gastel, NL;

Antonio Corradi, Eindhoven, NL;

Pieter Joseph Marie Wöltgens, Veldhoven, NL;

Assignee:

ASML Netherlands B.V., Veldhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/398 (2020.01); G03F 7/20 (2006.01); G06F 30/394 (2020.01); G06F 119/08 (2020.01); G06F 119/10 (2020.01); G06F 119/12 (2020.01); G06F 119/22 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G03F 7/70491 (2013.01); G03F 7/7055 (2013.01); G03F 7/70483 (2013.01); G06F 30/30 (2020.01); G06F 30/394 (2020.01); G06F 2119/08 (2020.01); G06F 2119/10 (2020.01); G06F 2119/12 (2020.01); G06F 2119/18 (2020.01); G06F 2119/22 (2020.01);
Abstract

A method for controlling a processing apparatus used in a semiconductor manufacturing process to form a structure on a substrate, the method including: obtaining a relationship between a geometric parameter of the structure and a performance characteristic of a device including the structure; and determining a process setting for the processing apparatus associated with a location on the substrate, wherein the process setting is at least partially based on an expected value of the geometric parameter of the structure when using the processing setting, a desired performance characteristic of the device and an expected physical yield margin or defect yield margin associated with the location on the substrate.


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