The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Jul. 29, 2019
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Wangyang Zhang, Allison Park, PA (US);

Elias Lee Fallon, Allison Park, PA (US);

Regis R. Colwell, Gibsonia, PA (US);

Hua Luo, Pittsburgh, PA (US);

Namita Bhushan Rane, Pittsburgh, PA (US);

Sheng Qian, Sunnyvale, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/39 (2020.01); G06N 20/00 (2019.01);
U.S. Cl.
CPC ...
G06F 30/39 (2020.01); G06N 20/00 (2019.01);
Abstract

The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and an electronic design layout and training a model using at least one predictor associated with the electronic design layout. Embodiments may further include obtaining an updated model, based upon, at least in part, the training. Embodiments may also include applying the updated model to a second electronic design schematic or a second electronic design layout, wherein one or more hard constraints or one or more soft constraints or both are created, based upon, at least in part, the model.


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