The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2021
Filed:
Sep. 28, 2017
Intel Corporation, Santa Clara, CA (US);
Dan Pritsker, San Diego, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A systolic array implemented in circuitry of an integrated circuit, includes a processing element array having processing elements arranged in a vertical direction and a horizontal direction, first loaders communicatively coupled to the processing element array to load samples Afrom at least one external memory to the processing element array, and second loaders communicatively coupled to the processing element array to load samples Bfrom the at least one external memory to the processing element array. Each row of the samples Ais loaded one row at a time to a single processing element along the horizontal direction, and each row of the samples Bis loaded one row at a time to a single processing element along the vertical direction, wherein pairing between the samples Aand Bin the horizontal direction and the vertical direction enables data reuse to reduce bandwidth usage of the external memory.