The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 2021

Filed:

Feb. 25, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stephen T. Palermo, Chandler, AZ (US);

Gerald Rogers, Chandler, AZ (US);

Shih-Wei Roger Chien, Shanghai, CN;

Namakkal Venkatesan, Portland, OR (US);

Rajesh Gadiyar, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 12/0815 (2016.01); G06F 12/0875 (2016.01); G06F 12/0811 (2016.01); G06F 9/50 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/3877 (2013.01); G06F 9/45529 (2013.01); G06F 9/50 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0875 (2013.01); G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 13/4027 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45595 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0058 (2013.01); G06F 2213/0064 (2013.01);
Abstract

Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.


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