The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2021
Filed:
Jun. 17, 2020
Cadence Design Systems, Inc., San Jose, CA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
The embodiments described herein provide for a method and system for implementing a multi-tap hybrid-equalization technique devoid of ISI jitter and PSI jitter in the high-speed data path to achieve 24 Gbps operating speed in systems utilizing GDDR6 DRAM. The method includes receiving an original data signal at a first TFFE circuit and receiving an altered data signal at a second TFFE circuit. The method further comprises generating a time-domain-equalized original data signal using a set of TFFE coefficients from the original data signal. The method further comprises generating a time-domain-equalized altered data signal using the set of TFFE coefficients from the altered data signal. The method further comprises generating, a time-and-voltage-domain-equalized data signal from the time-domain-equalized original data signal and the time-domain-equalized altered data signal at a voltage-feed forward equalization (VFFE) circuit using a set of VFFE coefficients.