The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Nov. 16, 2018
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Andreas Riegler, Lichtpold, AT;

Christian Fachmann, Fuernitz, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H02M 7/06 (2006.01); H02M 7/00 (2006.01); H02M 1/42 (2007.01);
U.S. Cl.
CPC ...
H01L 23/49562 (2013.01); H01L 21/4825 (2013.01); H01L 21/4839 (2013.01); H01L 21/78 (2013.01); H01L 23/3107 (2013.01); H01L 23/4951 (2013.01); H01L 23/49558 (2013.01); H01L 23/49575 (2013.01); H01L 23/49551 (2013.01); H01L 23/49568 (2013.01); H02M 1/4225 (2013.01); H02M 7/003 (2013.01); H02M 7/06 (2013.01);
Abstract

A package and a corresponding method are described. The method includes: providing a processed first wafer having front and back sides and including power semiconductor dies implemented within the wafer by processing its front side, each die having a first load terminal at the front side and a second load terminal at the back side; providing an unprocessed second wafer made of an electrically insulating material and having first and second opposing sides; forming a plurality of recesses within the second wafer; filling the plurality of recesses with a conductive material; forming a stack by attaching, prior or subsequent to filling the recesses, the second wafer to the front side of the first wafer, the conductive material electrically contacting the first load terminals of the power semiconductor dies; and ensuring that the conductive material provides an electrical connection between the first side and the second side of the second wafer.


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