Method of modeling high speed channel in semiconductor package, method of designing semiconductor package using the same and method of manufacturing semiconductor package using the same

Abstract

A method of modeling a high speed channel in a semiconductor package, the high speed channel including a plurality of first connection wirings on an upper surface of a semiconductor substrate and a plurality of through electrodes penetrating the semiconductor substrate, includes: receiving design information of the high speed channel, dividing the design information into a first layout including the plurality of first connection wirings and a second layout including the plurality of through electrodes; performing a first modeling operation on the first layout using a first modeling scheme and a first modeling tool; performing a second modeling operation on the second layout using a second modeling scheme, a second modeling tool, and at least a portion of the first layout; and obtaining an integrated modeling result of an entirety of the high speed channel by combining results of the first and second modeling operations.