The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Nov. 28, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Michael Kazda, Poughkeepsie, NY (US);

Harald Folberth, Boeblingen, DE;

Paul G. Villarrubia, Austin, TX (US);

Stephan Held, Bonn, DE;

Pietro Saccardi, Bonn, DE;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/30 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/30 (2020.01); G06F 30/392 (2020.01);
Abstract

To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.


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