The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 03, 2021
Filed:
Mar. 30, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Venkatraman Iyer, Austin, TX (US);
Darren S. Jue, Sunnyvale, CA (US);
Jeff Willey, Timnath, CO (US);
Robert G. Blankenship, Tacoma, WA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 13/16 (2006.01); G06F 1/12 (2006.01); G06F 13/40 (2006.01); H04L 12/933 (2013.01); H04L 12/741 (2013.01);
U.S. Cl.
CPC ...
G06F 13/161 (2013.01); G06F 1/12 (2013.01); G06F 13/1673 (2013.01); G06F 13/4004 (2013.01); G06F 13/4068 (2013.01); G06F 13/4221 (2013.01); H04L 45/74 (2013.01); H04L 49/15 (2013.01);
Abstract
A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.