The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 2021

Filed:

Mar. 29, 2019
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Tetsuya Iida, Ibaraki, JP;

Yasutaka Nakashiba, Ibaraki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); H01S 5/02345 (2021.01); H01L 31/12 (2006.01); H01L 31/0232 (2014.01); H01L 31/18 (2006.01); H01S 5/02326 (2021.01); H01S 5/02 (2006.01); H01S 5/026 (2006.01); H01S 5/40 (2006.01); H01S 5/02375 (2021.01); H01S 5/042 (2006.01); H01S 5/028 (2006.01); H01L 31/02 (2006.01);
U.S. Cl.
CPC ...
G02B 6/12004 (2013.01); H01L 31/02005 (2013.01); H01L 31/02327 (2013.01); H01L 31/12 (2013.01); H01L 31/186 (2013.01); H01S 5/02345 (2021.01); G02B 2006/12061 (2013.01); G02B 2006/12121 (2013.01); G02B 2006/12123 (2013.01);
Abstract

According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.


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