The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Apr. 30, 2020
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventor:

Zhaomeng, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 21/266 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66681 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/76237 (2013.01); H01L 29/0634 (2013.01); H01L 29/0653 (2013.01); H01L 29/0865 (2013.01); H01L 29/0882 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/66659 (2013.01); H01L 29/7816 (2013.01);
Abstract

A semiconductor structure and a forming method thereof are provided. One form of the forming method includes: providing a base, where a well region and a drift region adjacent to the well region are formed in the base; forming a trench in the drift region; forming a diffusion barrier layer in the trench; after the diffusion barrier layer is formed, forming a gate structure on the base at a junction between the well region and the drift region, where the gate structure is located on a side of the diffusion barrier layer near the well region; and forming a source region in the well region on one side of the gate structure, and forming a drain region in the drift region on the other side of the gate structure, where the drain region is located on a side of the diffusion barrier layer in the drift region away from the well region. In embodiments and implementations of the present disclosure, during the operation of the semiconductor structure, under the barrier action of the diffusion barrier layer, doping ions in the drain region do not easily diffuse into the channel region below the gate structure, which makes a depletion layer of the source region and the drain region on two sides of the gate structure not easily expand, thereby being beneficial to alleviate the short-channel effect, and further improving the electrical performance of the semiconductor structure.


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