The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 27, 2021
Filed:
Apr. 17, 2019
International Business Machines Corporation, Armonk, NY (US);
Zuoguang Liu, Schenectady, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Oleg Gluschenkov, Tannersville, NY (US);
Muthumanickam Sankarapandian, Niskayuna, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Self-aligned gate/junction for VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: forming a stack on a wafer including a first c-SiGe layer, a c-Si layer, and a second c-SiGe layer, wherein the first c-SiGe layer serves as a bottom source/drain; forming fin hardmasks on the stack; partially recessing the second c-SiGe layer to form a fin(s) in the second c-SiGe layer, wherein the second c-SiGe layer that is partially recessed/fin(s) serve as a top source/drain; amorphizing the c-Si layer to form a-Si regions in between c-Si regions that serve as vertical channels; selectively removing the a-Si regions to form gate trenches; forming bottom/top spacers in the gate trenches; and forming gates in the gate trenches that are offset from the bottom/top source/drain by the bottom/top spacers. A VTFET device is also provided. The VTFET device is suitable for 3D monolithic integrated circuits.