The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Jun. 21, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyung-Hwa Yun, Hwaseong-si, KR;

Pan-Suk Kwak, Seoul, KR;

Chan-Ho Kim, Seoul, KR;

Bong-Soon Lim, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 27/11573 (2017.01); G11C 16/08 (2006.01); H01L 27/24 (2006.01); G11C 16/04 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01); G11C 11/56 (2006.01); H01L 27/11582 (2017.01); G11C 7/04 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11573 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 7/04 (2013.01); G11C 11/5678 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 13/0028 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H01L 27/11582 (2013.01); H01L 27/249 (2013.01); H01L 45/06 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/52 (2013.01); G11C 2213/71 (2013.01); G11C 2213/72 (2013.01); G11C 2213/76 (2013.01); G11C 2213/77 (2013.01); H01L 27/2427 (2013.01); H01L 45/126 (2013.01); H01L 45/144 (2013.01);
Abstract

A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.


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