The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2021

Filed:

Mar. 25, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Josh Lin, Tainan, TW;

Chia-Ta Hsieh, Tainan, TW;

Chen-Ming Huang, Tainan, TW;

Chi-Wei Ho, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 27/11519 (2017.01); H01L 27/11531 (2017.01); H01L 23/485 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/76802 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 27/11519 (2013.01); H01L 27/11526 (2013.01); H01L 27/11531 (2013.01); H01L 29/42324 (2013.01); H01L 29/6653 (2013.01); H01L 23/485 (2013.01); H01L 29/6656 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip having a flash gate structure disposed over a substrate and including a control gate separated from a floating gate by an inter-electrode dielectric. One or more first sidewall spacers laterally surround the flash gate structure. The inter-electrode dielectric is directly between the one or more first sidewall spacers. A logic gate structure is disposed over the substrate and is laterally surrounded by one or more second sidewall spacers having a smaller height than the one or more first sidewall spacers.


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